Why hardware FIR filters (FIR filters) are doing the FFT?

Probably a very stupid question, but the direct answer I never found. For example given the task to design conveyor hardware FIR filter (FIR-filter), for example on 1024 points. Why usually do it using FFT (Fast Fourier transform, FFT), and not in the forehead by the formula of convolution? It would seem each successive step of the conveyor does not increase the clock frequency and the area increases linearly. Isn't it?

Maybe somewhere there is info on this subject?
October 3rd 19 at 02:40
2 answers
October 3rd 19 at 02:42
In the conveyor method the speed is determined by the critical (slowest) the area between the memory elements. So if you do just by definition, there does not appear any critical places. It confuses me... - vance.Beier commented on October 3rd 19 at 02:45
October 3rd 19 at 02:44
I can not quite in the subject, but where this is the case? And hardware FIR is usually not projecting, he is already inside the crystal, you only need to configure. And so there is an assumption that one and the same unit, considering FFT is used for filters, convolution, FFT/DCT, to save space on the chip
I probably put nothing category "Microcontrollers". I'm interested in is the design of hardware filter within the FPGA, or even ASIC.

Well, for example, OpenCores is the implementation using FFT:
opencores.org/project,fft_fir_filter - vance.Beier commented on October 3rd 19 at 02:47
I did so habrahabr.ru/post/134485/
fir filter in the forehead, the memory for the coefficients, a shift register for the data, a multiplier accumulator, a conveyor for the length of the coefficients, the OC input into the coefficients length of time. - vance.Beier commented on October 3rd 19 at 02:50

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