the first MK gives 8bit, the second MK 8 bits, and latches the register.
I need to generate 40MHz (VGA)
It seems you need a video DAC (aka video encoder), it's about the way it works. For example, the THS8200
. More options from Analog Devices
But to generate the initial data flow is hardly possible to do with a set of small controllers, you also have the original data still forming, not just output. Although to display the statics of can and ride.
Better suited for this FPGA, the processor may generate the image and give it to Pliska, and that, in turn, is engaged exclusively in its conclusion. The data will be quite a lot, so you can store them in external RAM connected to the FPGA.
PS take a Look at the Altera DE-1
on this Board already have a simple R2R DAC on VGA output.