How to implement a traffic light in vhdl?

Hello. The task to implement traffic lights. 10 seconds one led is lit (red), then for 3 seconds lights up one led(red+yellow), then green for 5 seconds, then 3 seconds flashes with a duty ratio of 2 and turning red.
Got this code(without flashing yet), but the project is going. I can not understand his mistake. I hope for your help. Thank you
here is the code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee. std_logic_arith.all;

entity course is 
port
(
 srst : in std_logic;
 clk : in std_logic; --NOW
 dout : out std_logic_vector (2 downto 0) --OUTPUT the state of the traffic light
);
end entity;

architecture Behavioral of course is
TYPE state_type IS (RED,YELLOW,GREEN,GREEN_M);
signal next_state, state : state_type; --SIGNALS WHERE the DATA is STORED ON the STATE of the TRAFFIC light
signal enR,enG,enGM,enY, enCR, enCG, enCY, enCGM, led : std_logic;
signal counterR,counterY,counterG, counterGM : std_logic_vector (29 downto 0):= (others => '0');
signal tempout : std_logic_vector (2 downto 0);

lab72 component is
Port ( clk : in STD_LOGIC;
dout : out STD_LOGIC);
end component lab72;

begin

process (state, enR, enY, enG enGM) begin
next_state<=RED;
case state is
 when RED =>
 enCR <= '1';
 if(enR='1') then 
 next_state <= YELLOW; 
 else 
 next_state <= RED;
 end if;

 when YELLOW => 
 enCY <= '1'; -- TOGGLE GREEN 
 if(enY='1') then
 next_state <= GREEN; 
else
 next_state <= YELLOW;
 end if; 

 when GREEN =>
 enCG <= '1';
 if(enG='1') then
next_state<=GREEN_M;
else
 next_state <= GREEN;
 end if;

 when GREEN_M=>
 enCGM <= '1';
 if (enGM='1') then
next_state<=RED;
else
 next_state <= GREEN_M;
 end if;

 when others =>
 next_state <= RED;
end case; 
end process;

process(clk) begin
if rising_edge(clk) then
state<=next_state;
end if;
end process;

process (clk) begin
 if rising_edge(clk) then
 if unsigned(counterR)=1000000000 then
 counterR <= (others => '0');
enR<='1';
 elsif (enCR ='1') then
 counterR <= unsigned(counterR)+1; 
enR<='0';
 end if; 
 end if;
end process;

process (clk) begin
 if rising_edge(clk) then
 if unsigned(counterY)=300000000 then
 counterY <= (others => '0');
enY<='1';
 elsif (enCY ='1') then
 counterY <= unsigned(counterY)+1; 
enY<='0';
 end if; 
 end if;
end process;

process (clk) begin
 if rising_edge(clk) then
 if unsigned(counterG)=500000000 then
 counterG <= (others => '0');
enG<='1';
 elsif (enCG='1') then
 counterG <= unsigned(counterG)+1; 
enG<='0';
 end if; 
 end if;
end process;

process (clk) begin
 if rising_edge(clk) then
 if unsigned(counterGM)=300000000 then
 counterGM <= (others => '0');
enGM<='1';
 elsif (enCGM='1') then
 counterGM <= unsigned(counterGM)+1; 
enGM<='0';
 end if; 
 end if;
end process;

out_proc : process (state) begin --definition output

tempout (2 downto 0) <= (others =>'0');

 if (state) = RED then
 tempout(2 downto 0) <= "001";
 elsif (state) = YELLOW then
 tempout(2 downto 0) <= "011";
 elsif (state) = GREEN then
 tempout(2 downto 0) <= "100";
 elsif (state) = GREEN_M then
 tempout(2 downto 0) <= led & "00";
 end if;
end process;

process (clk) begin --reset
 if rising_edge(clk) then
 if srst = '1' then
 state <= RED;
 enCR <= '1';
 dout(0) <= '1' ;
else
 state <= next_state;
 dout <= tempout; 
 end if;
 end if;
end process;

end Behavioral;
April 3rd 20 at 18:45
0 answer

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