Questions tagged [VHDL] (24)

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Where can I learn VHDL in Russian?

Hello. Interesting hardware description language - VHDL. Please tell me where can I learn VHDL, in Russian, thank you in advance.
Shanel asked April 9th 20 at 09:55
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How to get the synthesized and optimized netlist in Quartus 2?

Quartus2 can in different ways to convert a program in vhdl to netlist. It all depends on the settings. Also in the program for verification is embedded rtl viewer. But this is purely a built-in thing and file it contains pure rendering but I need a connection file, which will show the entire program, including libraries, s...
eleazar.Morissette15 asked April 4th 20 at 00:51
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How to implement a traffic light in vhdl?

Hello. The task to implement traffic lights. 10 seconds one led is lit (red), then for 3 seconds lights up one led(red+yellow), then green for 5 seconds, then 3 seconds flashes with a duty ratio of 2 and turning red. Got this code(without flashing yet), but the project is going. I can not understand his mistake. I hope for...
esperanza asked April 3rd 20 at 18:45
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VHDL for beginners

Not so long ago I started to get interested in FPGA and, accordingly, to explore this unusual language. It so happened that I want to share with the public, but the ambush... In connection with the introduction of new rules to publish the finished article I can't :) The public will be interested in reading? If Yes, then ple...
Moshe.Rolfson8 asked October 10th 19 at 00:26
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Processing/cleaning "multilingual" source

You want to make the VHDL code obfuscation, but due to lack of direct funds for this task, you can use any custom obfuscator that would remove the comments do AutoCorrect word list on the file list. Most importantly, to be able to tell him what words are key, and they did not touch to. Well, the comment was to indicate wha...
eveline_Gottlieb asked October 9th 19 at 15:55
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Will it help to speed up the work OS hardware scheduler?

What do you think is appropriate, and most importantly is it possible a significant increase in performance OS, if you create a hardware task scheduler? Who will manage the scheduling of threads, synchronization tools, etc., thereby relieving the CPU. All this is applied to operational real-time systems and systems-on-chip....
terrence asked October 3rd 19 at 02:07
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Plugin for dynamic syntax highlighting VHDL

My task is to create an online editor VHDL code. On the Internet I ran across a shitload of plugins for syntax highlighting of various languages(including VHDL), however, none of the dynamic(codemirror, EditArea, etc.). does not support the backlight that is VHDL. It is necessary that the code was highlighted in the process...
Isai.Kozey asked October 2nd 19 at 19:37
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How to get rid of errors [Route 35-39] The design did not meet timing requirements when wiring the device to the FPGA?

IDE Vivado from Xilinx gives out here's a critical warning: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports. The Report Timing Summary shows that the signal clk inside one of the blocks so divorced that does not meet timing. How can you get rid of this error? ...
terrence asked September 30th 19 at 20:09
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How to learn programming FPGA?

Please advise books/tutorials/MOOC on programming of the FPGA. There are many books that explain the syntax Verilog HDL/VHDL, but they do not describe how best to describe the logic. The hands on rutracker there are a few books, a La "Advanced something with Verilog", but it is also a little something. Need is something in ...
Wava_Gislason asked September 27th 19 at 00:42
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How to connect two microblaze processor to the same memory (BRAM) in Xilinx Vivado?

Please write to those who have experience connecting two microblaze to one memory module via LMB? I want to make so that the program memory was shared (was in the same range adreev), and RAM was separate (from each processor its own range of addresses). And so how. the program memory is shared, the code I'm going to associa...
terrence asked September 27th 19 at 00:39